O_基于FE11S的4位2_0_USB_HUB

源生, 电子硬件

O_嵌入式专题目录

源文件请至 S_MZ公开库 查看。

更新中……

V2_03_220410

功能介绍

SCH

PCB

V1_01_201028

功能介绍

  • 500mA-1A电流输出能力
  • 每一路工作指示及PPTC保护
  • MicroUSB与TypeC并存

SCH

PCB

  • 实测要把R13去掉，否则电脑读不出来，芯片内部前端1.5K上拉，后端15K下拉，数据手册写了没注意到
  • 实测读取速率能到22MB/S，写入速度平均在4MB/S左右

　
> - 休眠功能正常，具体多长时间没实际测试过，实测大约10分钟吧，设计的时候应该是看到过相关的说明，现在再翻手册又找不到了….

　

知识储备

USB 文档

USB 2.0接口标准的三种速度规格

High-speed 25Mbps～400Mbps(最大480Mbps) (高速 HIGH-SPEED)
Full-speed 500Kbps～10Mbps(最大12Mbps)（全速 FULL-SPEED）
Low-speed 10Kbps～100Kbps(最大1.5Mbps)（低速 LOW-SPEED）
（如果高速设备接在USB1.X的hub上，也只能工作在全速状态。）

低速设备在D-上有1.5K的上拉电阻。
全速设备在D+上有1.5K的上拉电阻。
高速设备在D+上有1.5K的上拉电阻，在全速模式下与集线器进行握手，握手成功进入高速模式，否则为全速模式。

USB2.0 高速模式握手

  High-speed devices begin the enumeration process as full-speed devices. During the reset phase, high-speed devices and high-speed capable hubs begin a negotiation process to determine if they can mutually move into the high-speed mode. This process starts by asserting a voltage on D+ and D- and is shown in detail in the following diagram:

Device “Chirp”
  During reset, a high-speed device will assert a 17.8 mA signal on D- for at least 1 ms. This causes the hub to see a voltage of 0.8 V on D-. If the hub is high-speed capable, it will respond. Low-speed and full-speed only hubs will ignore this signal.

Hub’s K-J Chirp Response
  Within 100 μs of detecting the device chirp, a high-speed capable hub will respond with a series of alternating K-J chirps. Each chirp is 50 μs long.

Device Response
  After three consecutive K-J chirps are detected, the device will connect a termination load on D+ and D-, allowing the system to conduct high-speed communications. The hub will continue to send K-J chirps until just before the reset sequence is terminated.

End of Reset Sequence
  When the reset sequence concludes, the device and the port on the hub will be operating in high-speed mode.

以上摘于：Detecting a High-Speed USB Device - Microchip Developer Help

USB2.0 详细电气配置

7.1.5.1 Low-/Full-speed Device Speed Identification
  The USB is terminated at the hub and function ends as shown in Figure 7-20 and Figure 7-21. Full-speed and low-speed devices are differentiated by the position of the pull-up resistor on the downstream end of the cable:

  • Full-speed devices are terminated as shown in Figure 7-20 with the pull-up resistor on the D+ line.

  • Low-speed devices are terminated as shown in Figure 7-21 with the pull-up resistor on the D- line.

  • The pull-down terminators on downstream facing ports are resistors of 15 kΩ ±5% connected to ground.

  The design of the pull-up resistor must ensure that the signal levels satisfy the requirements specified in Table 7-2. In order to facilitate bus state evaluation that may be performed at the end of a reset, the design must be able to pull-up D+ or D- from 0 V to VIH (min) within the minimum reset relaxation time of 2.5 μs. A device that has a detachable cable must use a 1.5 kΩ ±5% resistor tied to a voltage source between 3.0 V and 3.6 V (VTERM) to satisfy these requirements. Devices with captive cables may use alternative termination means. However, the Thevenin resistance of any termination must be no less than 900 Ω.

  Note: Thevenin resistance of termination does not include the 15 kΩ ±5% resistor on host/hub. The voltage source on the pull-up resistor must be derived from or controlled by the power supplied on the USB cable such that when VBUS is removed, the pull-up resistor does not supply current on the data line to which it is
attached.

7.1.5.2 High-speed Device Speed Identification
  The high-speed Reset and Detection mechanisms follow the behavioral model for low-/full-speed. When reset is complete, the link must be operating in its appropriate signaling mode (low-speed, full-speed, or high-speed as governed by the preceding usage rules), and the speed indication bits in the port status register will correctly report this mode. Software need only initiate the assertion of reset and read the port status register upon notification of reset completion.

  High-speed capable devices initially attach as full-speed devices. This means that for high-speed capable upstream facing ports, RPU (1.5 kΩ ±5%) must be connected from D+ to the 3.3 V supply (as shown in Figure 7-1) through a switch which can be opened under SW control.

  After the initial attachment, high-speed capable transceivers engage in a low level protocol during reset to establish a high-speed link and to indicate high-speed operation in the appropriate port status register. This protocol is described in Section 7.1.7.5.






Δt1 This is the amount of time required for the hub port power switch to operate. This delay is a function of the type of hub port switch. Hubs report this time in the hub descriptor (see Section 11.15.2.1), which can be read via a request to the Hub Controller (see Section 11.16.2.4). If a device were plugged into a nonswitched or already-switched on port, Δt1 is equal to zero.

Δt2 (TSIGATT) This is the maximum time from whenVBUS is up to valid level (4.01 V) to when a device has to signal attach. Δt2 represents the time required for the device’s internal power rail to stabilize and for D+ or D- to reach VIH (min) at the hub. Δt2 must be less than 100 ms for all hub and device implementations. (This requirement only applies if the device is drawing power from the bus.)

Δt3 (TATTDB) This is a debounce interval with a minimum duration of 100 ms that is provided by the USB System Software. It ensures that the electrical and mechanical connection is stable before software attempts to reset the attached device. The interval starts when the USB System Software is notified of a connection detection. The interval restarts if there is a disconnect. The debounce interval ensures that power is stable at the device for at least 100 ms before any requests will be sent to the device.

Δt4 (T2SUSP) Anytime a device observes no bus activity, it must obey the rules of going into suspend (see Section 7.1.7.6).

Δt5 (TDRST) This is the period of time hubs drive reset to a device. Refer to Section 7.1.7.5 and Section 11.5.1.5 for details.

Δt6 (TRSTRCY) The USB System Software guarantees a minimum of 10 ms for reset recovery. Device response to any bus transactions addressed to the default device address during the reset recovery time is undefined.

阻抗匹配

总结：低速和全速时最好进行阻抗匹配，源端串联或终端并联90ohm±15%，高速时不需要。

USB电平：

  • 电源线是5V，为USB设备提供最大500mA的电流，它与数据线上的电平无关。
  • 数据线是差分信号，通常 D+ 和 D- 在 +400mV~-400mV 间变化。当D+比D-大200mV时为1，D+比D-小200mV时为0。在低速和全速的时候是电压驱动型,而在高速的时候是电流驱动型的,所以在高速的时候不要传入电阻.

  网上所说的匹配电阻都是在全速和低速模式下的，低速、全速模式下为电压驱动的，驱动器具有一定输出阻抗(一般较小)，USB线的特性阻抗为90ohm所以要想源端与USB线匹配就需要串电阻，具体阻值是要根据驱动器的输出阻抗来决定的，即要求源端差分阻抗=USB线差分特性阻抗；而要终端匹配的话就需要并联电阻了(终端的阻抗一般很大)，在驱动能力不强的情况下根本就没法实现；至于匹配电阻要放在源端还是终端，因为USB是双向的，所以要匹配源端的话则应串在源端，要匹配终端的话则并联放在终端。

  在低速和全速模式下是电压驱动的，驱动电压为3.3V，但在高速模式下是电流驱动的，驱动电流为17.78mA，接入匹配电阻反而会降低信号的质量。

– 摘自USB的阻抗匹配问题 - CSDN

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