JTAG与SWD
JTAG
JTAG（Joint Test Action Group，联合测试工作组）是一种国际标准测试协议（IEEE 1149.1兼容），主要用于芯片内部测试。现在多数的高级器件都支持JTAG协议，如DSP、FPGA器件等。标准的JTAG接口是4线：TMS、TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。
JTAG的三大功能：
- 下载器，即下载软件到FLASH里。
- DEBUG，跟医生的听诊器似的，可探听芯片内部小心思。
- 边界扫描，可以访问芯片内部的信号逻辑状态，还有芯片引脚的状态等等。
JTAG根本没有标准的接口定义，甚至每家公司定义都不一样，具体参见 IEEE 1149.1 - JTAG 。
在JTAG接口中，最常用的信号有四个，分别是TCK/TMS/TDO/TDI。JTAG接口可以一对一的使用，也可以组成菊花链的一对多拓扑结构，两种拓扑结构如下图所示。多核的芯片，其芯片内部已经接成了菊花链的形式。
SWD
SWD全称Serial Wire Debug，是ARM为嵌入式设备推出的一种简单的调试接口，这种接口通过一条双向数据线和一条时钟线实现对于ARM核心的调试。
2-Pin Debug Port
Serial Wire Debug (SWD) provides a debug port for severely pin-limited packages, often the case for small package microcontrollers but also complex ASICs, where limiting pin count is critical and can be the controlling factor in device costs.
SWD replaces the 5-pin JTAG port with a clock + single bi-directional data pin, providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the processor or requiring any target resident code. SWD uses an Arm standard bi-directional wire protocol, defined in the Arm Debug Interface v5, to pass data to and from the debugger and the target system in a highly efficient and standard way. As a standard interface for Arm processor-based devices, the software developer can count on a wide choice of interoperable tools from Arm and third party tool vendors.
- Only 2 pins required - vital for very low connectivity devices or packages.
- Provides debug and test communication to JTAG TAP controllers.
- Enables the debugger to become another AMBA bus master for access to system memory and peripheral or debug registers.
- High performance data rates - 4 Mbytes/sec @ 50 MHz.
- Low power - no extra power or ground pins required.
- Small silicon area - 2.5k additional gates.
- Low tools costs, $100 build costs - may be built in to evaluation boards.
- Reliable - built in error detection.
- Safe - protection from glitches on pins when tools are not connected.
- SWD provides an easy and risk-free migration from JTAG as the two signals, SWDIO and SWCLK, are overlaid on the TMS and TCK pins, allowing for bi-modal devices that provide the other JTAG signals. These extra JTAG pins are available for other uses when in SWD mode.
SWD is compatible with all Arm processors and any processor using JTAG for debug and provides access to debug registers in Cortex processors (A, R, and M) and the CoreSight debug infrastructure.
Serial Wire technology is today a part of mass production devices such as the ST® STM32 microcontroller.
Single Debug Port for Multi-Chip Products
Arm Multi-drop SWD technology brings the benefits of SWD to complex, multi-processor-based SoCs by enabling simultaneous access to an unlimited number of devices through a single connection, providing complex-device developers with a low power 2-pin debug and trace solution. This is particularly important for connectivity-constrained products, such as mobile phones, where multi-die and multiple chips are common.
The Multi-drop SWD is fully backwards compatible, retaining existing single point-to-point host equipment connections, and permits a device to power down completely while that device is not selected, reducing power consumption. Serial Wire debug with multi drop support is available to all CoreSight licensees under their maintenance program.
SWD uses only two signals :
SWDCLK. The clock signal sent by the host. As there is no relation between the processor clock and the SWD clock, the frequency selection is up to the host interface. In this KB article, the maximum debug clock frequency is about 60MHz but varies in practice.
SWDIO. This is the bidirectional signal carrying the data from/to the DP. The data is set by the host during the rising edge and sampled by the DP during the falling edge of the SWDCLK signal.
Both lines should be pulled up on the target.
拓展 - ARM Debug Interface
Contrary to JTAG, which chains TAPs together, SWD uses a bus called DAP (Debug Access Port). On this DAP, there is one master (the DP – Debug Port) and one or more slaves (AP – Access Ports), similar to JTAG TAPs. The DP communicates with the APs using packets that contain the AP address.
To sum this up, an external debugger connects to the DAP via the DP using a protocol called SWD. This whitepaper from ARM shows a nice overview of the SWD architecture :
Debug ports
The Debug Port is the interface between the host and the DAP. It also handles the host interface. There are three different Debug Ports available to access the DAP :
JTAG Debug Port (JTAG-DP). This port uses the standard JTAG interface and protocol to access the DAP.
Serial Wire Debug Port (SW-DP). This port uses the SWD protocol to access the DAP.
Serial Wire / JTAG Debug Port (SWJ-DP). This port can use either JTAG or SWD to access the DAP. This is a common interface found on many microcontrollers. It reuses the TMS and TCK JTAG signals to transfer the SWDIO and SWDCLK signals respectively. A specific sequence has to be sent in order to switch from one interface to the other.
Access Ports
Multiple APs can be added to the DAP, depending on the needs. ARM provides specifications for two APs :
Memory Access Port (MEM-AP). This AP provides access to the core memory aand registers.
JTAG Access Port (JTAG-AP). This AP allows to connect a JTAG chain to the DAP.
拓展 - SWIM
SWIM接口主要用于于ST的STM8系列单片机，ST-Link2与STM8连接只需要4根线，SWIM接口只需要一根传输线，即可完成双向的传输。传输过程，都是由主控制端（host)发起，设备端然后做出反应。host端需要在一个总线上实现读和写，那就是说必须要同时接一个输出IO和一个输入IO（也可以用同一个，开漏的情况下，IO可以同时读写）,且输出IO必须设计成开漏，总线上挂接上拉电阻，以便随时交出控制权。
JLink
J-Link是SEGGER公司为支持仿真ARM内核芯片推出的JTAG仿真器。配合IAR EWAR，ADS，KEIL，WINARM，RealView等集成开发环境支持所有ARM7/ARM9/ARM11，Cortex M0/M1/M3/M4，Cortex A5/A8/A9等内核芯片的仿真，与IAR，Keil等编译环境无缝连接，操作方便、连接方便、简单易学，是学习开发ARM最好最实用的开发工具。产品规格：电源USB供电，整机电流<50mA支持的目标板电压1.2～3.3V，5V兼容目标板供电电压4.5～5V（由USB提供5V）目标板供电电流最大300mA，具有过流保护功能。工作环境温度+5℃～+60℃存储温度-20℃～+65℃湿度<90%尺寸（不含电缆）100mmx53mmx27mm重量（不含电缆）70g电磁兼容EN 55022，EN 5502。
JLink OB
The J-Link OB (for On-Board) is essentially a microcontroller-based, single-chip, J-Link that goes right on the evaluation board. It is compatible with, and has the same features as, J-Link BASE with reduced, but still great, performance.
The microcontroller that is used as a J-Link OB (on the left side of the evaluation board in the diagram below) has a USB-interface on its left side (facing the host) and a JTAG/SWD + SWO interface on its right side (facing the target device).
Connecting the PC and the target CPU using a regular J-Link.
Connecting the PC and the target CPU using a J-Link OB.
关于JLink OB其他的介绍及可用的核心：J-Link OB - SEGGER
STLink
STM8和STM32的ST-LINK/V2在线调试器/编程器，接口为ARM-JTAG接口，具体接口定义请参考本文 JLink 引脚图。
The ST-LINK/V2 is an in-circuit debugger and programmer for the STM8 and STM32 microcontrollers. The single-wire interface module (SWIM) and JTAG/serial wire debugging (SWD) interfaces are used to communicate with any STM8 or STM32 microcontroller located on an application board. In addition to providing the same functionalities as the ST-LINK/V2, the ST-LINK/V2-ISOL features digital isolation between the PC and the target application board. It also withstands voltages of up to 1000 Vrms.
ULink
ULINK已经停产，在售的是ULINK2和ULINKpro版本，ULINK2是ARM/KEIL公司（2005年ARM收购了KEIL）最新推出的配套RealView MDK使用的仿真器。
ULINK2
ULINK2 is an entry-level debugger for Cortex-M devices. Control the processor, set breakpoints, and read/write memory contents, all while the processor is running at full speed.
ULINKplus
ULINKplus combines isolated debug connection, power measurement, and I/O for test automation. Function, timing, and power consumption visibility enables developers to optimize applications further.
ULINKpro
This sophisticated unit enables developers to program, debug and analyze applications using high-speed streaming trace. Required for code coverage and performance analysis.
对比图源自：教麦叔了解J-Link、ST-Link、ULink、JTAG、SWD、SWIM的区别 - 记得诚 - CSDN
CMSIS-DAP
CMSIS-DAP provides a standardized way to access the Coresight Debug Access Port (DAP) of an ARM Cortex microcontroller via USB. CMSIS-DAP is generally implemented as an on-board interface chip, providing direct USB connection from a development board to a debugger running on a host computer on one side, and over JTAG (Joint Test Action Group) or SWD (Serial Wire Debug) to the target device to access the Coresight DAP on the other.
CMSIS-DAP is a specification and a implementation of a Firmware that supports access to the CoreSight Debug Access Port (DAP).
The various Arm Cortex processors provide CoreSight Debug and Trace. CMSIS-DAP supports target Devices that contain one or more Cortex processors. A Device provides a Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD) interface that connects to a Debug Unit. CMSIS-DAP is the interface firmware for a Debug Unit that connects the Debug Port to USB. Debuggers that execute on a host computer connect via USB and the Debug Unit to the Device which runs the application software.
CMSIS-DAP Overview
The CMSIS-DAP Firmware version 2 can be configured in two different USB interface modes:
- Version 1 configuration uses USB HID as interface to the host PC.
- Version 2 configuration uses WinUSB as interface to the host PC and provides high-speed SWO trace streaming.
Benefits of CMSIS-DAP:
- Provides a standardized interface for debuggers. Interfaces to many standard debuggers is available.
- Access to CoreSight registers of all Cortex processor architectures (Cortex-A/R/M).
- Connects via 5-pin JTAG or 2-pin Serial Wire Debug (SWD).
- Supports multi-core debugging.
- Supports Serial Wire Output of Cortex-M devices (new in CMSIS-DAP Version 1.1.0).
- Easy to deploy to Debug Units based on Cortex-M microcontrollers.
- Debug Unit may be integrated on an evaluation board.
- USB using HID (Human Interface Device) driver class that avoids driver installation on host PC.
- Supports time-critical JTAG or SWD command execution (new in CMSIS-DAP Version 1.10).
- Supports Test Domain Timer for time measurement using the debug unit (new in CMSIS-DAP Version 1.2.0)
The CMSIS-DAP Firmware is provided as source code and is fully configurable to a new Debug Unit. A source code template and several reference implementations for popular Debug Units are provided. Refer to Firmware Configuration for more information.
The CMSIS-DAP Software Stack is composed of the following components:
- CMSIS-DAP Firmware that interfaces to JTAG or SWD Debug pins using standard I/O pins of the Cortex-M device.
- CMSIS-Driver USART that connects the UART of the Cortex-M device to the SWO output from the target.
- USB Communication Stack that interfaces to the USB Port of the Host Computer using the HID or custom class.
- The USB Device middleware may require CMSIS-RTOS and a CMSIS-Driver USB.
CMSIS-DAP Software Stack
- 关于 CMSIS-DAP Firmware 。
- 关于 CMSIS-DAP Debugger 。
- 目前官方已将调试工具升级为DAPLink，详见下节。
DAPLink
DAPLink是ARM官方开源的一款调试烧录器，以前叫CMSIS DAP，现在改名叫DAPLink，同时在功能上也大大提高了。DAPLINK可以调试Arm Cortex全系列MCU，所以相比STLINK和JLink这方面更有优势。官方的维护一直在更新，未来也会扩充更多功能进来。DAPLink的开源地址：https://github.com/ARMmbed/DAPLink 。
DAPLINK主要功能：
- Arm-Cortex芯片的调试和烧录（HID）
- 自带虚拟串口，省去USB转串口（CDC）
- 拖拽式编程，模拟出U盘，hex或者bin拷贝进行完成烧录（MSC）
- WEBUSB功能（固件要升级到2050）
关于U盘拖拽式编程：
通过USB把DAPLink插上电脑以后会识别出来一个U盘（U盘名称不同版本可能会有区别，但是使用是一样的）。把hex或者bin文件拷贝进U盘中，就可以把代码烧录进目标芯片的Flash中。这是通过把烧录Flash算法嵌入DAPLink固件中来实现的，所以目前每个DAPLink固件只能支持一种特定目标芯片进行烧录。如果想实现其他芯片的拖拽功能，可以更换固件。
关于虚拟串口功能：
DAPLink连接电脑以后也会识别出来一个串口。该串口在不同的操作系统下名称是不同的：在Windows下面叫做COM口，可以到设备管理器查看；Linux系统下是作为一个 /dev/tty 出现的；MAC系统识别为/dev/usbmodem。当使用Linux或者MAC系统时不需要安装任何驱动，Win10下也不需要安装，但假如使用Win7或者Win8需要安装串口驱动。该驱动下载地址。
关于WEBUSB功能：
WebUsb是DAPLink添加的新功能（请更新到2050及以上版本固件），通过WebUsb可以在浏览器中识别出来USB设备，意味着可以在浏览器里面轻松烧录和调试代码。Arm也推出dap.js，这是一套针对CMSIS-DAP协议的Javascript接口。这样就可以通过nodejs或浏览器轻松使用WebUsb功能。dap.js的开源地址如下：https://github.com/ARMmbed/dapjs 。